The present invention relates to a data processing device and, more particularly, to a technology which is effective if applied to a central processing unit of a single-chip microcomputer.
The single-chip microcomputer is classified into microcomputers of 4 bits, 8 bits and 16 bits in accordance with the data length which is handled mainly by their central processing units (as will be shortly referred to as "CPU"). Of these, the 8-bit single-chip microcomputer is most frequently used at present and is packaged to control a device. This 8-bit single-chip microcomputer is exemplified by H8/330 HD6473308 HD 6433308 Hardware Manual Hitach Ltd., published August 1989, the English version of which correspondes to Hitachi Single-Chip Microcomputer H8/330 HD6473308, HD6433308 Hardware Manual, 1st Edition, December 1989. The central processing unit of the 8-bit single-chip microcomputer (as will be called the "8-bit CPU") has a data length of 8 bits to be mainly handled so that the 8-bit CPU has a register or accumulator having a length of 8 bits and a register of 16 bits having a length twice as long as that of the 8-bit register. This 8-bit CPU uses mainly the 8-bit register or the register of 16 bits mainly for processing data and only the 16-bit register as an address register for referring to a memory, although not especially limitative thereto. The 16-bit register as such address register may be called the "index register", "stack pointer" or "program counter".
The aforementioned 8-bit CPU is given 16 bits (i.e., 2 bytes) as its minimum unit of instruction. On the other hand, in case an instruction or data of 16 bits is to be arranged in the memory, it is so limited that it is arranged in an area of 2 bytes continuing from an even number. Moreover, the operation instruction of the aforementioned 8-bit CPU is made effective only between the registers in the CPU, and the data arranged in the memory have to be manipulated in response to the operation instruction after they have been once transferred to the register in the CPU. Despite of this limit, the internal construction of the CPU, i.e., the construction of the control unit for controlling the execution of the CPU is simplified to realize a reduction in the logical and physical scales. This reduction in the logical and physical scales is effective to reduce the manufacture cost. As a secondary effect, it is possible to improve the operation speed. In other words, a relatively high processing performance can be realized at a relatively low manufacture cost.